FlexIC Platform Gen 3
Pragmatic FlexIC Platform Gen 3 delivers rapid design and manufacture of mixed-signal ASICs
Benefits
What makes it so great
Thin and flexible chips for novel applications
Standard electronic design automation (EDA) tool compatibility
Standard cell library to accelerate design success
Rapid fabrication on 300mm wafers, reducing time to market
Sustainable, low-carbon manufacturing
Platform Gen 3 gives a 10x digital power and 3x digital area improvement over the previous generation. Take a deep dive into the technical specifications with SVP Technology Catherine Ramsdale.
Want to know how Platform Gen 3 makes it quick and easy to design mixed-signal ASICs in FlexIC technology? Discover the process design kit with Senior Director, Design Platform, Dave Verity.
Built on a flexible substrate, Platform Gen 3 offers a 600 nm minimum channel dimension n-type FET, a dedicated 200 kΩ/sq resistor layer and 4.5 fF/μm2 metal-insulator-metal capacitors. Four metal layers provide efficient routing and interconnects, with a 4 μm routing pitch and 1 μm line width/spacing.
The technology is packaged with passivation for protection and isolation, and a redistribution layer (RDL) with aluminium metallisation for compatible attachment methods.
Ready to start designing?
Request the PDK
Everything you need for design success, from technology data and rules files to device models compatible with leading EDA simulation tools.
Want to know more?
Download the product brief
Get the detail you need, from full technical specifications to features and benefits.
What process technology does Pragmatic FlexIC Platform Gen 3 use?
What process technology does Pragmatic FlexIC Platform Gen 3 use?
It’s based on 600nm Indium Gallium Zinc Oxide (IGZO) thin-film transistor (TFT) NMOS process technology.
What’s in the PDK?
What’s in the PDK?
- Primitive device library with simulation models
- Parameterized cells (PCells)
- Verification checks (DRC, LVS)
- Technology data and files
- Design, layout, tape out manuals & guides
Is the PDK compatible with industry-standard EDA tools?
Is the PDK compatible with industry-standard EDA tools?
Yes, Cadence and Siemens.
How thin are FlexICs?
How thin are FlexICs?
Around 37 microns, including wafer-level packaging.
How flexible are they?
How flexible are they?
They have a minimum bend radius of just 5mm.
How are they made?
How are they made?
Using proven, conventional semiconductor processing equipment and techniques such as photolithography on 300mm wafer carriers. The substrate preparation differs from silicon semiconductor fabrication and the number of process steps is significantly lower.