After winning Best Paper at MICRO-58, one of the world’s premier conferences on microarchitecture, ASIC Design Engineers Alireza Raisiardali and Konstantinos Iordanou explain how their award-winning research – Flexing RISC-V Instruction Subset Processors (RISSPs) to the Extreme Edge – enables the rapid, automated creation of custom processors for flexible electronics.
Efficiency is an essential requirement of any microcontroller unit (MCU). But for applications at the ‘extreme edge’ – the smart objects that constitute the Internet of Everything – cost, form factor, and sustainability are also defining factors.
To meet these requirements, we propose a way to automatically generate low-cost, low-carbon and physically flexible processors for extreme edge workloads, based on RISC-V instruction set architecture and Pragmatic’s FlexIC technology platform.
When implemented as FlexICs, RISSPs can achieve up to 42% area and 21% power savings compared to the full RISC-V processor. They are also up to 40 times more energy efficient than the smallest existing 32-bit RISC-V processor.
The methodology is unique because verification is an integral part of design.
So how does it work?
Tinier, quicker, more cost-effective
Our research essentially takes the open-source RISC-V architecture and breaks it down into small ‘building blocks’ of instructions. Each instruction is treated as a discrete, fully functional, pre-verified hardware block.
A high-level hardware design description of the extreme edge application is converted into a functional layout, generating the RISC-V instructions – typically a subset of the full RISC-V instruction set. The selected instructions are then ‘stitched’ together to create a custom processor. The RISC-V instructions that are not used by the application are not implemented in the RISSP generation methodology, so reducing size, area and complexity.
Because each instruction hardware block is already pre-verified, this approach dramatically reduces design and verification time, making it quicker and more cost-effective to create processors tailored to specific tasks.
The processor can then be fabricated on Pragmatic’s FlexIC technology platform. The platform’s unique, low-temperature production method is based on a polyimide substrate rather than the silicon typical of most microchips. This gives the chips physical flexibility, an industry-leading carbon footprint – and the low cost-point necessary for many extreme edge applications.
Read more about FlexICs’ sustainability in our report (PDF)
Powering the ‘extreme edge’
Extreme edge devices are designed to sense, compute, and connect right at the point of use – in everyday items such as packaging, clothing, or even medical products.
Some products are designed for single or limited use – in smart packaging or asset-tracking labels, for example. Their built-in electronics are part of the product and are disposed of when the item is replaced.
In these mass-market applications, cost and sustainability are critical: each chip might need to cost just a few cents to make sense commercially, and the materials must be environmentally responsible.
In short, these are not tasks for traditional silicon chips. These multi-purpose powerhouses are typically too expensive, take too long to develop and carry an outsized carbon footprint.
That’s why flexible electronics – low-carbon, low-cost and quick to produce at scale – are emerging as the ideal solution. They make it possible to add intelligence to billions of everyday objects sustainably and affordably, paving the way for truly connected, data-rich environments.
Realising the Internet of Everything
This work shows what’s possible when flexibility meets innovation. By combining the open-source RISC-V with the sustainability and scalability of FlexIC technology, we’re redefining what’s possible at the extreme edge.
It’s not just about making chips smaller or cheaper – it’s about proliferating intelligence everywhere, unlocking the power of a truly sustainable Internet of Everything.
Read the full paper on ACM Digital Library: Flexing RISC-V Instruction Subset Processors to Extreme Edge
